The subject matter relates to a semiconductor design technology, and more particularly, to a phase detector circuit. Especially, the subject matter relates to a phase detector circuit of a semiconductor device, said circuit having an improved phase detection ability through a phase detection operation synchronized with an external clock
In general, a synchronous semiconductor memory device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) includes a phase detector circuit for detecting a phase difference between clocks although the clocks have different frequencies or the same frequencies.
FIG. 1 is a diagram showing a conventional phase correction circuit according to the related art.
Referring to FIG. 1, the conventional phase correction circuit includes a phase detector 100 for detecting a phase difference between a main clock CLOCK_PC and a sub clock CLOCKB_PC in response to a strobe signal STROBE, and a duty ratio corrector 120 for correcting a duty ratio of the main clock CLOCK_PC and the sub clock (CLOCKB_PC) in response to output signals UP/DOWN_SIG and VALID_STROBE of the phase detector 100. The phase correction circuit according to the related art further includes a phase correction operation controller 140 for controlling a phase correction operation by generating an enable signal ENABLE to control On/Off the operation of the duty ratio corrector 120 and phase detector 100.
The duty ratio corrector 120 includes a code counter 122 for increasing or decreasing a duty correction code DUTY_CORRECTION_CODE in response to the output signals UP/DOWN_SIG and VALID_STROBE of the phase detector 100, and a phase controller 124 for controlling phases of a main clock CLOCK_PC and a sub clock CLOCKB_PC in response to the duty correction code DUTY_CORRECTION_CODE.
Hereinafter, operation of the conventional phase correction circuit will be described based on the above described structure.
When the phase correction operation controller 140 activates the enable signal ENABLE, the phase controller 100 and the duty ratio corrector 120 are enabled to perform their respective operations.
In this condition, if the phase correction operation controller 140 starts to toggle a strobe signal STROBE at a regular interval, the phase detector 100 accordingly starts detecting a phase difference between a main clock CLOCK_PC and a sub clock CLOCKB_PC.
The phase detector 100 outputs an activated phase detection signal UP/DOWN_SIG if the phase of the sub clock CLOCKB_PC is larger than that of the main clock CLOCK_PC. Alternatively, the phase detector 100 outputs a deactivated phase detection signal UP/DOWN_SIG if a phase of the main clock CLOCK_PC is larger than that of the sub clock CLOCKB_PC.
At the same time, the phase detector 100 outputs activate or inactivate valid detection signal VALID_STROBE. Here, the valid detection signal VALID_STROBE indicates whether the phase detection signal UP/DOWN_SIG outputted from the phase detector 100 is valid or invalid.
The phase detector 100 performs a phase detection operation in response to a strobe signal STROBE toggled at a regular interval. That is, the phase detector 100 performs a phase detection operation and outputs the phase detection signal UP/DOWN_SIG whenever a strobe signal STROBE is toggled. However, the phase detector 100 cannot detect an accurate phase difference of the main clock CLOCK_PC and the sub clock CLOCKB_PC by one time toggling of the strobe signal STROBE. That is, an accurate phase difference between the main clock CLOCK_PC and the sub clock CLOCKB_PC can be detected by repeating the phase detection operation by toggling the strobe signal STROBE several times. Accordingly, if the duty ratio corrector 120 were to use phase detection signal UP/DOWN_SIG whenever the strobe signal STROBE was toggled, it would not perform an accurate phase correction operation. Instead, accurate phase correction operation is performed by having the duty ratio corrector 120 uses the phase detection signal UP/DOWN_SIG when the valid detection signal VALID_STROBE is active.
The coding counter 122, included in the duty ratio corrector 120, increases or decreases a duty correction code DUTY_CORRECT_CODE in response to a phase detection signal UP/DOWN_SIG applied when the valid detection signal VALID_STROBE is active.
For example, if the phase detection signal UP/DOWN_SIG is active when the valid detection signal VALID_STROBE is in an active state, this indicates that a detected phase of a sub clock CLOCKB_PC is greater than the phase of the main clock CLOCK_PC. In response, the coding counter 122 increases and outputs the duty correction code DUTY_CORRECT_CODE. If the phase detection signal UP/DOWN_SIG is inactive, the detected phase of the main clock CLOCK_PC is less than the phase of the sub clock CLOCKB_PC. In response, the coding counter 122 decreases and outputs the duty correction code DUTY_CORRECT_CODE.
A predetermined initial value for the duty correction code DUTY_CORRECT_CODE is defined in advance.
The phase controller 124, included in the duty ratio controller 120, drives an external main clock CLOCK and an external sub clock CLOCKB with a driving power corresponding to the duty correction code DUTY_CORRECT_CODE and outputs them as the main clock CLOCK_PC and the sub clock CLOCKB_PC.
For example, if the value of the duty correction code DUTY_CORRECT_CODE is comparatively large, the external main clock CLOCK is driven stronger than the external sub clock CLOCKB and outputted as the main clock CLOCK_PC and the sub clock CLOCKB_PC. If the value of the duty correction code DUTY_CORRECT_CODE is comparatively small, the external sub clock CLOCKB is driven stronger than the external main clock CLOCK and outputted as the main clock CLOCK_PC and the sub clock CLOCKB_PC.
Although the main clock CLOCK_PC and the sub clock CLOCKB_PC output by the duty ratio corrector 120 may also be input and used in an internal circuit of a semiconductor device using the main clock CLOCK_PC and the sub clock CLOCKB_PC, the main clock CLOCK_PC and the sub clock CLOCKB_PC are inputted to the phase detector 100 and used for performing a phase correction operation.
The phase difference between the external main clock CLOCK and the external sub clock CLOCKB is not accurately corrected through only one phase correction operation. The main clock CLOCK_PC and the sub clock CLOCKB_PC with the phase difference accurately corrected are output through repetition of the phase correction operations.
FIG. 2 is a circuit diagram showing a phase detector 100 included in the conventional phase correction circuit of FIG. 1.
Referring to FIG. 2, the phase detector 100 includes a first voltage output unit 102 for outputting a first voltage OUTB having a potential level varying corresponding to a duty ratio of a main clock CLOCK_PC, a second voltage output unit 104 for outputting a second voltage OUT having a potential level varying corresponding to a duty ratio of a sub clock CLOCKB_PC, and a potential level comparator 106 for comparing the potential levels of the first voltage OUTB and the second voltage OUT and generating a phase detection signal UP/DOWN_SIG and a valid detection signal VALID_STROBE according to the result thereof.
Hereinafter, the operation of the phase detector 100, included in the conventional the phase correction circuit, will be described based on the above described structure thereof.
The operation of the first voltage output unit 102 and the second voltage output unit 104 may be divided into a ‘charge operation period’ and a ‘discharge operation period’ according to a strobe signal STROBE.
That is, the potential levels of the first voltage OUTB and the second voltage OUT increase because first and second strobe PMOS transistor ST_P1 and ST_P2 are turned on and a strobe NMOS transistor ST_N is turned off when the strobe signal STROBE is inactive, at a logical low. Here, the first and second strobe PMOS transistors ST_P1 and ST_P2 respectively control applying power to an output end OUT_ND1 of the first voltage output unit 102 and an output end OUT_ND2 of the second voltage output unit 104. The strobe NMOS transistor ST_N directly controls power discharge. That is, since the first voltage output unit 102 and the second voltage output unit 104 perform an operation for raising the potential levels of the first voltage OUTB and the second voltage OUT, the operation thereof is the charge operation period.
In the charge operation period, the potential levels of the first voltage OUTB and the second voltage OUT smoothly increase within a predetermined power level variation width by first and second load capacitors LOAD_CAP1 and LOAD_CAP2, although the output end OUT_ND1 of the first voltage output unit 102 and the output end OUT_ND2 of the second voltage output unit 104 are directly connected to a power voltage end VDD. And, the first and second load capacitors respectively connected to the output end OUT_ND1 of the first voltage output unit 102 and the output unit OUT_ND2 of the second voltage output unit 104.
Here, the main clock CLOCK_PC and the sub clock CLOCKB_PC cannot influence the increment of the potential levels of the first and second voltage OUTB and OUT although the logical levels of the main clock CLOCK_PC and the sub clock CLOCKB_PC are changed. In the charge operation period of the first and second voltage output units 102 and 104, the potential levels of the first and second voltages OUTB and OUT increase as much as a predetermined potential level regardless of the logical levels of the main clock CLOCK_PC and the sub clock CLOCKB_PC.
And, the potential levels of the first and second voltages OUTB and OUT decrease because the first and second strobe PMOS transistor ST_P1 and ST_P2 are turned off and the strobe NMOS transistor ST_N is turned on when the strobe signal STROBE is activated to logical high. Here, the first and second strobe PMOS transistor ST_P1 and ST_P2 directly control applying power to an output end OUT_ND1 of the first voltage output unit 102 and an output end OUT_ND2 of the second voltage output unit 104. The strobe NMOS transistor ST_N controls power discharge. That is, it is the discharge operation period because the first and second voltage output units 102 and 104 perform operations for decreasing the potential levels of the first and second voltages OUTB and OUT.
In the discharge operation period, the potential levels of the first and second voltages OUTB and OUT gradually decrease with a predetermined potential level variation width by the first and second load capacitors LOAD_CAP1 and LOAD_CAP2 connected to the output end OUT_ND1 of the first voltage output unit 102 and the output end OUT_ND2 of the second voltage output unit 104 although the output end OUT_ND1 of the first voltage output unit 102 and the output end OUT_ND2 of the second voltage output unit 104 are directly connected a ground voltage end VSS.
Here, a time of decreasing the potential levels of the first and second voltages OUTB and OUT is changed according to logical level variation of the main clock CLOCK_PC and the sub clock CLOCKB_PC.
In more detail, if the main clock CLOCK_PC is activated to logical high, the potential level of the first voltage OUTB outputted from the first voltage output unit 120 decreases. If the main clock CLOCK_PC is inactivated to logical low, the potential level of the first voltage OUTB outputted from the first voltage output unit 102 does not decrease if the main clock CLOCK_PC is inactivated to logical low.
If the sub clock CLOCKB_PC is active, at a logical high, the potential level of the second voltage OUT output from the second voltage output unit 104 decreases. If the sub clock CLOCKB_PC is inactive, at a logical low, the potential level of the second voltage OUT output from the second voltage output unit 104 does not decrease.
In a period where the logical level of the strobe signal STROBE is inactive, at a logical low, the potential level of the first voltage OUTB and the potential level of the second voltage OUT increase as much as the same level. However, a period where the logical level of the strobe signal STROBE is active, at a logical high, the potential level of the first voltage OUTB gradually decreases corresponding to the activation period of the main clock CLOCK_PC and the potential level of the second voltage OUT also gradually decreases corresponding to the activation period of the sub clock CLOCKB_PC. Therefore, the potential level of the first voltage OUTB and the potential level of the second voltage OUT decrease as much as different potential levels.
Here, if the phase correction operation controller 140 repeats an inactivation period of the strobe signal STROBE where the strobe signal STROBE is inactivated to logical low at a predetermined interval by controlling the inactivation period of the strobe signal STROBE longer than an activation period thereof, a potential level of a voltage corresponding to one the main clock CLOCK_PC and the sub clock CLOCKB_PC having a longer activation period will decrease more. Therefore, it is possible to detect which between the main clock CLOCK_PC and the sub clock CLOCKB_PC has a longer activation period. In this way, it is possible to compare a phase of the main clock CLOCK_PC and a phase of a sub clock CLOCKB_PC.
Also, since the first voltage output unit 102 and the second voltage output unit 104 are formed in a cross-coupled formation, a potential level difference of the first and second voltages OUTB and OUT is not great due to an activation period difference of the main clock CLOCK_PC and the sub clock CLOCKB_PC when the logical level variation of the strobe signal STROBE repeats as many as initial regular times. However, if the potential level difference of the first and second voltages OUTB and OUT becomes larger than a predetermined level difference, the potential level is abruptly amplified, thereby reaching a potential level of the power source voltage VDD and a potential level of the ground voltage VSS.
That is, the first voltage OUTB has the same potential level of the ground voltage VSS and the second voltage OUT has the same level of the power source voltage VDD finally, even if the potential level of the second voltage OUT is slightly higher than the potential level of the first voltage OUTB when the logical level of the strobe signal STROBE varies for the initial predetermined times and when the activation period of the main clock CLOCK_PC is longer than the activation period of the sub clock CLOCKB_PC. Finally,.
Similarly, the potential level of the second voltage OUT becomes the same potential level of the ground voltage VSS and the level of the first voltage OUTB becomes the same level of the power source voltage VDD finally, even if the potential level of the first voltage OUTB is slightly higher than the potential level of the second voltage OUT when the logical level of the strobe signal STROBE varies for the initial predetermined times and when the activation period of the sub clock CLOCKB_PC is longer than the activation period of the main clock CLOCK_PC.
The potential level comparator 106 activates or inactivates a phase detection signal UP/DOWN_SIG according to the potential level difference between the first voltage OUTB and the second voltage OUT and outputs the activated or the inactivated phase detection signal. Also, the potential level comparator 106 activates or inactivates a valid detection signal VALID_STROBE.
For example, the potential level comparator 106 activates and outputs the phase detection signal UP/DOWN_SIG when the potential level of the first voltage OUTB is greater than that of the second voltage OUT, indicating that the detected phase of the main clock CLOCK_PC is greater than that of the sub clock CLOCKB_PC. The potential level comparator 106 inactivates the phase detection signal UP/DOWN_SIG if the potential level of the first voltage OUTB is less than that of the second voltage OUT, indicating that the detected phase of the sub clock CLOCKB_PC is smaller than the phase of the main clock CLOCK_PC.
If a logical level, e.g., High or Low corresponding to the potential level of the first voltage OUTB is identical to a logical level corresponding to a potential level of the second voltage OUT when the potential levels of the first and second voltages OUTB and OUT are changed to a logical level based on a logical decision level at the same time, the potential level comparator 106 inactivates and outputs the valid detection signal VALID_STROBE. If the logical levels are different, the potential level comparator 106 activates and outputs the valid detection signal VALID_STROBE.
As described above, the phase detector 100 of the conventional phase correction circuit performs the phase detection operation by comparing the potential levels of the first voltage OUTB corresponding to an activation period of the main clock CLOCK_PC and the second voltage OUT corresponding to an activation period of the sub clock CLOCKB_PC.
Meanwhile, the phase detector 100 of the conventional phase correction circuit performs a phase detection operation in response to a strobe signal STROBE that is not synchronized with external clocks CLOCK and CLOKCB.
As the phase correction operation controller toggles and outputs the strobe signal STROBE at a regular interval, regardless of toggling of the external clocks CLOCK and CLOCKB, the phase detector 100 performs the phase detection operation by changing the potential levels of the first and second voltages OUTB and OUT in response to the toggled strobe signal from the phase correction operation controller 140.
The resulting potential levels of the first and second voltages OUTB and OUT are different because the potential level of the first voltage OUTB is changed corresponding to the activation period of the main clock CLOCK_PC and the potential level of the second voltage OUT is changed corresponding to the activation period of the sub clock CLOCKB_PC. An assumption is that if the phase of the main clock CLOCK_PC is different from the phase of the sub clock CLOCKB_PC, the length of the activation period of the main clock CLOCK_PC is different from the length of the activation period of the sub clock CLOCKB_PC.
However, the phase detector 100 of the phase correction circuit according to the related art may have the following problems if the operation of the phase detector 100 is controlled as described above.
FIG. 3 is a timing diagram illustrating the operation of a phase detector of a phase correction circuit shown in FIG. 1.
Referring to FIG. 3, the timing diagram clearly shows that the strobe signal STROBE has a frequency lower than those of the main clock CLOCK_PC and the sub clock CLOCKB_PC applied to the phase detector 100.
That is, during a period that the strobe signal is toggled one time, the main clock CLOCK_PC and the sub clock CLOCKB_PC are toggled many times.
Here, the phase detector 100 of the conventional phase correction circuit cannot be aware of a transition time of the strobe signal because the strobe signal STROBE is a clock not synchronized with the external clocks CLOCK and CLOCKB which are clocks synchronized with the main clock CLOCK_PC and the sub clock CLOCKB_PC.
As shown in the first case, the strobe signal STROBE is activated before the main clock CLOCK_PC is inactivated after the main clock CLOCK_PC is activated and before the sub clock CLOCKB_PC is activated after the sub clock CLOCKB_PC is inactivated. After the strobe signal STROBE is activated, the strobe signal STROBE may be inactivated before the main clock CLOCK_PC is activate after the main clock CLOCK_PC is inactivated and before sub clock CLOCKB_PC is activated after the sub clock CLOCKB_PC is inactivated.
As shown in the second case, the strobe signal STROBE is activated before the main clock CLOCK_PC is activated after the main clock CLOCK_PC is inactivated and before the sub clock CLOCKB_PC is inactivated after the sub clock CLOCKB_PC is activated. After the strobe signal STROBE is activated, the strobe signal STROBE is inactivated before the main clock CLOCK_PC Is activated after the main clock CLOCK_PC is inactivated and before the sub clock CLOCKB_PC is activated after the sub clock CLOCKB_PC is inactivated.
If the activation periods of the strobe signal STROBE are setup like the first and second cases of the timing diagram, the periods of sustaining the active state of the main clock CLOCK_PC are smaller than the periods of sustaining the active state of the sub clock CLOCKB_PC in number in the first case.
In the second case, the periods of sustaining an active state of the main clock CLOCK_PC is larger than the periods of sustaining an active state of the sub clock CLOCKB_PC in number.
Thus, if the number of the periods of sustaining the active state of the main clock CLOCK_PC and the number of the periods of sustaining the inactive state of the sub clock CLOCKB_PC are changed because the activation periods of the strobe signal STROBE are wrongly defined, the phase detector 100 of the phase correction circuit according to the related art wrongly recognizes that a length of an activation period of one clock is longer than the other regardless of the actual lengths of the activation periods of the main clock CLOCK_PC and the sub clock CLOCKB_PC, thereby outputting an incorrect phase detection operation result.
Such a problem may frequently arise when the phase difference between the main clock CLOCK_PC and the sub clock CLOCKB_PC, which are applied to the phase detector 100 of the conventional phase correction circuit, is comparatively small.
Also, the problem may frequently arise when the frequency of the main clock CLOCK_PC and the sub clock CLOCKB_PC, which are applied to the phase detector 100 of the phase correction circuit according to the related art, is high.
Since the phase detection operation is the major operation of the phase correction circuit, a correct phase correction operation cannot be expected if the phase detection operation returns a wrong result. Also, if an internal circuit of a semiconductor device performs a predetermined operation using the wrong phase detection result, it is also difficult to expect that the semiconductor device returns an accurate and correct result.